1. Field of the Invention
The present invention relates to a solid-state imaging device, and an electronic module and an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
A solid-state imaging device including a large number of pixels arrayed in a two-dimensional matrix has been widely known. Each pixel has photo-electric conversion elements including a photodiode.
A CMOS (Complementary Metal-Oxide-Semiconductor) solid-state imaging device and a CCD (Charge-Coupled Device) solid-state imaging device are such solid-state imaging devices having respective read and transfer methods.
In particular, CMOS solid-state imaging devices with excellent characteristics have been developed in accordance with a recent progress of semiconductor manufacturing process and have attracted an attention.
FIG. 1 is a schematic diagram showing an arrangement of a CMOS solid-state imaging device according to the related art. As shown in FIG. 1, a CMOS solid-state imaging device 101 includes a first conductivity type, for example, N-type silicon semiconductor substrate 102 on which a second conductivity type, that is, P type semiconductor well region 103 is formed. The P-type semiconductor well region 103 includes a photodiode 105 serving as a photo-electric conversion element and a MOS transistor group 106 formed of a plurality of MOS transistors in a unit pixel area divided by a pixel separating area 110.
The photodiode 105 is formed of an N-type semiconductor area surrounded by the pixel separating area 110 and the P-type semiconductor well region 103. Specifically, the photodiode 105 is formed of a low-impurity concentration N-type semiconductor region (N− semiconductor region) 111 located deep from the surface and a high-impurity concentration N-type semiconductor region (N+ semiconductor region) 112 located at the surface side. Further, a P+ accumulation layer 113 formed of a high-impurity concentration P-type semiconductor region is formed on an interface at the surface side of the N+ semiconductor region 112 so as to suppress occurrence of a dark current. The photodiode 105 is configured as a HAD (Hole Accumulation Diode) sensor.
The MOS transistor group 106 includes a read transistor 107 connected to the photodiode and other MOS transistors 108.
The read transistor 107 is formed of an N+ source/drain region 114 formed in the P-type semiconductor well region 103, the N+ semiconductor region 112 of the photodiode 105 and a gate electrode 118 formed on a substrate surface between the N+ source/drain region 114 and the photodiode 105 through a gate insulated film.
The other MOS transistors 108 are formed of the N+ source/drain regions 115 and 116 formed in the P-type semiconductor well region 103 and a gate electrode 119 formed on the substrate surface between the N+ source/drain regions 115 and 116 through a gate insulated film. When including four MOS transistors, a read transistor, a reset transistor, an amplification transistor and a vertical selection transistor are arranged, for example. Further, multilayer wiring layers 125 is formed on the substrate surface through an insulating interlayer 123. Also, a color filter and an on-chip lens (not shown) and so on are formed.
Light incident on the photodiode 105 is applied from the substrate surface side on which the MOS transistors for accumulating and reading signal charge are formed. Such surface-illuminated CMOS solid-state imaging device 101 includes an antireflective film to increase the efficiency of focusing to the photodiode 105 on the substrate surface side. The surface-illuminated CMOS solid-state imaging device 101 typically includes four or more silicon oxide (SiO) films and silicon nitride (SiN) films forming a protective film to prevent the photodiode, the MOS transistor group and a wiring layer from being deteriorated with age and an insulating interlayer formed under the protective film on the photodiode 105.
Upon manufacturing such solid-state imaging device, if impurities such as metals, in particular, heavy metals are mixed into the semiconductor substrate, quality and characteristics of the manufactured semiconductor device may be deteriorated greatly.
Impurities may be mixed into the semiconductor substrate when water and various gases used in the process of manufacturing the semiconductor substrate contain impurities, or may be generated from members constituting an apparatus used in the process. It is difficult to completely eliminate such impurities and therefore it is difficult to manufacture a semiconductor substrate without impurities.
Therefore, “gettering” is carried out so as to remove impurities from the semiconductor substrate in the vicinity of the surface. Specifically, a gettering site having a function of capturing and fixing impurities mixed into the semiconductor substrate is formed within the semiconductor substrate and the gettering site captures and fixes impurities in the vicinity of the surface of the semiconductor substrate (see Japanese Unexamined Patent Application Publication No. 2006-93175, for example).
An intrinsic gettering (IG) of forming a gettering site as a layer within a semiconductor substrate and an extrinsic gettering (EG) of forming a gettering site at the rear surface of a semiconductor substrate are given as examples of such gettering.
However, the related-art arrangement having such gettering site alone is not sufficient in terms of gettering ability to capture and fix impurities. Also, there may be a risk that impurities once captured by the gettering site be drained later from the gettering site to the photodiode, and so a probability of generating a white spot may increase.